Publication: Design and Reuse

First reported 9 hours ago - Updated 9 hours ago - 1 reports

12G PHY, TSMC 28HPM x2, North/South (vertical) poly orientation

"The multiprotocol DesignWare Enterprise 12G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in enterprise applications. Using leading-edge design, analysis, simulation, and measurement ... [Published Design and Reuse - 9 hours ago]
First reported 14 hours ago - Updated 14 hours ago - 1 reports

Sub-1GHz ISM Transceiver

Silicon Vision, SVITRX402 is a highly integrated, low power, high performance multiband radio transceiver IP covering the 415/433/868/915/950MHz ISM bands (Industrial, Scientific and Medical) and compatible with IEEE 802.15.4G standard. SVITRX402 contains ... [Published Design and Reuse - 14 hours ago]
First reported Aug 29 2014 - Updated Aug 29 2014 - 1 reports

BIST schemes for ADCs

Kushal Kamal & Vandana Sapra (Qualcomm)EDN (August 29, 2014)With an increasing number of complex circuits being integrated into SoCs, their testing requirements have become equally complex. While there are well established test strategies for digital ... [Published Design and Reuse - Aug 29 2014]
Entities: QUALCOMM Inc, Strategy
First reported Aug 29 2014 - Updated Aug 29 2014 - 1 reports

New details on Altera network-on-FPGA

Advantages to using NoCs in SoC design are well documented: reduced routing congestion, better performance than crossbars, improved optimization and reuse of IP, strategies for system power management, and so on. What happens when NoCs move into FPGAs, ... [Published Design and Reuse - Aug 29 2014]
Entities: Altera Corp, Strategy
First reported Aug 29 2014 - Updated Aug 29 2014 - 1 reports

IoT Focus: Wrestling with the Design, Time to Market, and Cost Challenges of IoT

You know we live in astonishing times when you can start your car by talking into your phone. But the era of the Internet of Everything--for all the great technology it has begun to enable--is filled with challenges for electronics design engineers.C ... [Published Design and Reuse - Aug 29 2014]
First reported Aug 28 2014 - Updated Aug 28 2014 - 1 reports

Pinning down the acceptable level of jitter for your embedded design

Dean Smith, Integrated Device Technologyembedded.com (August 26, 2014)There are several clock jitter types, measurement methodologies, and corresponding specifications. But most hardware designers don’t have the time to research these, and the detailed ... [Published Design and Reuse - Aug 28 2014]
First reported Aug 28 2014 - Updated Aug 28 2014 - 2 reports

Google Selects Rockchip for Modular Smartphone Processor

Internet giant Google has started a design effort with Chinese fabless chip company Rockchip to develop an application processor for the Project Ara modular mobile phone, according to a posting within the Google+ interest group section for Google's Advanced ... [Published Design and Reuse - Aug 28 2014]
First reported Aug 28 2014 - Updated Aug 28 2014 - 1 reports

New MIPS Creator CI20 development board for Linux and Android debuts

With Imagination Blog - Alexandru VoicaFeatures a 1.2GHz MIPS-based, dual-core Ingenic apps processor that runs Debian 7 and Android 4.4 KitKatA few weeks ago, when I first published an article titled MIPS CPUs, the perfect Linux machines, the first question ... [Published Design and Reuse - Aug 28 2014]
Entities: Linux, Android, Debian
First reported Aug 28 2014 - Updated Aug 28 2014 - 1 reports

Embedded flash process enhances performance: Product how-to

Jae Song, Dongbu HiTekEDN (August 23, 2014)Mobile phones and tablets have become natural extensions of billions of users worldwide. Considered an essential companion by many, these gadgets continue to push performance limits as they integrate enhanced ... [Published Design and Reuse - Aug 28 2014]
First reported Aug 28 2014 - Updated Aug 28 2014 - 1 reports

SATA PHY, TSMC 90G, x2

see the entire datasheet get in contact with SATA PHY, TSMC 90G, x2 Supplier ... [Published Design and Reuse - Aug 28 2014]
First reported Aug 28 2014 - Updated Aug 28 2014 - 1 reports

Real-Time Ray Tracing GPU

RayCore 2000 is the latest real-time ray tracing GPU IP for high-performance, high-resolution mobile and embedded devices. This advanced GPU IP provides more immersive reality-like 3D contents to end-users and more convenience content development environment ... [Published Design and Reuse - Aug 28 2014]
First reported Aug 28 2014 - Updated Aug 28 2014 - 1 reports

Variable Non-power-of-two FFT

This circuit can perform any number of non-power-of-two and/or traditional power-of-two Fourier transforms, chosen at run-time (prime factor algorithm is not used). Programmability is derived from a new type of memory-based array implementation that avoids ... [Published Design and Reuse - Aug 28 2014]

Quotes

"The multiprotocol DesignWare Enterprise 12G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in enterprise applications. Using leading-edge design, analysis, simulation, and measurement techniques, the Enterprise 12G PHY delivers exceptional signal integrity and jitter performance that exceeds the standards’ electrical specifications."
...published an article titled MIPS CPUs, the perfect Linux machines, the first question I got from a lot of developers from the Linux community was: "When can I get access to a MIPS-based development board capable of running Linux and equipped with ?"
"The Memory product line represents the largest selection of silicon-proven, low risk, easy to integrate, embedded memory IP available today. Hundreds of memory compilers are available ranging from 250-nm to 65-nm and spanning many foundries to address the demanding requirements of density, speed and power. Three separate families of sub-megabit embedded memory compilers are architured under the Area, Speed, and Power (ASAP) Memory product line. The High-Density (HD) memories address the needs of many applications that are optimized for area; the High-Speed (HS) memories address the requirements of high-performance systems; and the Ultra-Low Power (ULP) memories address the needs of power-sensitive portable applications. The Ultra-Low-Power architecture involves using techniques such as self-timed clocking, clock-partitioning, reduced bit-line swing, and array banking to deliver the lowest possible power. Sophisticated power models based on SPICE provide detailed and accurate power models for system integration. End-of-cycle shut-off logic and the addition of a memory disable pin ensure zero quiescent current regardless of the state of the clock or input pins, thereby facilitating very low power consumption when the memory is idle. The advanced Ultra-Low-Power architecture has been in used for designs as long ago as 180-nm. The High-Density (HD) address the area sensitive needs required in today's competitive system-on-chip (SoC) design environment while leveraging design techniques to optimize area without compromising on quality and ensure accurate test chip validation. The High-Speed memory architecture leverages state-of-the-art circuit techniques and rigid design practices to ensure high-performance does not come as the price of quality. The advanced design techniques used ensure tight internal timing controls across all process corners, operating voltages and temperatures. Some of these advanced design techniques include high-speed sense amplifiers, fast clocking, and fast bit-line recovery, which contribute to achieving the high-speeds required by today's high-performance applications. The Memory System includes self-testable and repairable memories ranging in size from the smallest register files (RF) to the largest multi-megabit memories, or integrate with most third-party BIST engines."
..." The hours were grueling and he realized that "when you're sleeping under your desk, it's time to cut the cord." Lots of cords were cut at high-tech firms in 2001. He was RIFed (reduction in force) and went on his way...

More Content

All (165) | News (165) | Reports (0) | Blogs (0) | Audio/Video (0) | Fact Sheets (0) | Press Releases (0)
sort by: Date | Relevance
12G PHY, TSMC 28HPM x2, North/South (vertical) ... [Published Design and Reuse - 9 hours ago]
Sub-1GHz ISM Transceiver [Published Design and Reuse - 14 hours ago]
New details on Altera network-on-FPGA [Published Design and Reuse - Aug 29 2014]
BIST schemes for ADCs [Published Design and Reuse - Aug 29 2014]
IoT Focus: Wrestling with the Design, Time to M... [Published Design and Reuse - Aug 29 2014]
Pinning down the acceptable level of jitter for... [Published Design and Reuse - Aug 28 2014]
Google Selects Rockchip for Modular Smartphone ... [Published Design and Reuse - Aug 28 2014]
New MIPS Creator CI20 development board for Lin... [Published Design and Reuse - Aug 28 2014]
Google's Project Ara Is Science Fiction, Says C... [Published Design and Reuse - Aug 28 2014]
Bluetooth Dual Mode RF IP [Published Design and Reuse - Aug 28 2014]
Variable Non-power-of-two FFT [Published Design and Reuse - Aug 28 2014]
Real-Time Ray Tracing GPU [Published Design and Reuse - Aug 28 2014]
SATA PHY, TSMC 90G, x2 [Published Design and Reuse - Aug 28 2014]
Embedded flash process enhances performance: Pr... [Published Design and Reuse - Aug 28 2014]
High Density Register File 16K Sync Compiler, U... [Published Design and Reuse - Aug 28 2014]
CSR confirms approach from Microchip Technology... [Published Design and Reuse - Aug 28 2014]
Data Centers May Ride on ASICs [Published Design and Reuse - Aug 28 2014]
10 tips on being a consultant [Published Design and Reuse - Aug 28 2014]
HDL Design House New Verification Seminar in Au... [Published Design and Reuse - Aug 28 2014]
Sibridge Technologies expands to Europe [Published Design and Reuse - Aug 28 2014]
Fujitsu Presents HEVC HD Decoding SoC for Multi... [Published Design and Reuse - Aug 27 2014]
The Intricate Puzzle Known as Chip Design [Published Design and Reuse - Aug 26 2014]
SiliconArts May Disrupt Mobile Graphics [Published Design and Reuse - Aug 25 2014]
Report: India, China show interest in Korean an... [Published Design and Reuse - Aug 25 2014]
Video Codecs in Close Battle [Published Design and Reuse - Aug 25 2014]
Near Field Communication (NFC) IP core [Published Design and Reuse - Aug 25 2014]
Fixed-size streaming FFT [Published Design and Reuse - Aug 25 2014]
mCube Creates New "Ten Degrees" Subsidiary to F... [Published Design and Reuse - Aug 25 2014]
High Speed Leakage Control SRAM 512K Sync Compi... [Published Design and Reuse - Aug 22 2014]
Baseband USB Power Delivery PHY and Controller [Published Design and Reuse - Aug 21 2014]
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